Rainbow Electronics W90P710CDG - Manual (Page 466)

W90P710CD/W90P710CDG
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BITS DESCRIPTIONS
[31:8] RESERVED -
[7:0] BLL
8 bit Baud rate divider Latch Low byte register
This register combining with BLH and CBR determine internal
sampling clock frequency.
Bit 7 ~ 0: Baud rate divisor latch lower byte values. Default to be
1Fh.
Baud Rate Divider Latch Higher Byte (SCHI_BLH)
REGISTER ADDRESS R/W DESCRIPTION
RESET
VALUE
SCHI_BLH0
0XFFF8_5004
(DLAB = 1)
R/W Baud rate divisor Latch Higher byte Register 0 0x0000_0000
SCHI_BLH1
0XFFF8_5804
(DLAB = 1)
R/W Baud rate divisor Latch Higher byte Register 1 0x0000_0000
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
BLL[7:0]
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
BLH[7:0]