Rainbow Electronics W90P710CDG - Manual (Page 269)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 269 - Revision B2
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BITS DESCRIPTIONS
[18] VDBPP18SW
Video image 18bpp swap control bit
0=Swap Disable
1=Swap Enable
[17] VDHSWP
Video half-word swap control bit.
0 = Swap Disable
1 = Swap Enable
[16] VDBSWP
Video byte swap control bit.
0 = Swap Disable
1 = Swap Enable
[15:2] Reserved Reserved
[1:0] FIFOEN
FIFOs transfer data enable
x1 = FIFO1 transfer enable x0=FIFO1 transfer disable
1x = FIFO2 transfer enable 0x=FIFO2 transfer disable
FIFO Status Register (FIFOSTATUS)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
FIFOSTATUS 0xFFF0_8024 R FIFOs status 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved MASTERID
BITS DESCRIPTIONS
[31:2] Reserved Reserved
[1:0] MASTERID
Currently, the data bus master
01 = FIFO1 grant the bus
11 = FIFO2 grant the bus