Rainbow Electronics W90P710CDG - Manual (Page 540)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 541 - Revision B2
SD Control Register Map, continued
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
FB0_0
…..
FB0_127
0xFFF0_7400
…..
0xFFF0_75FC
R/W Flash Buffer 0
Undefined
FB1_0
…..
FB1_127 0xFFF0_7800
...
0xFFF0_79FC
R/W Flash Buffer 1 Undefined
LCDC Control Register Map
REGISTER ADDRESS R/W DESCRIPTION
RESET
VALUE
LCD Controller
LCDCON 0XFFF0_8000 R/W LCD Control 0x0000_0000
LCD Interrupt Control
LCDINTENB 0xFFF0_8004 R/W LCD Interrupt Enable 0x0000_0000
LCDINTS 0xFFF0_8008 R LCD Interrupt Status 0x0000_0000
LCDINTC 0xFFF0_800C W LCD Interrupt Clear 0x0000_0000
LCD Pre-processing
OSDUPSCF 0xFFF0_8010 R/W OSD Horizontal/Vertical up-scaling factor 0x0000_0000
VDUPSCF 0xFFF0_8014 R/W Video Horizontal/Vertical up-scaling factor 0x0000_0000
OSDDNSCF 0xFFF0_8018 R/W OSD Horizontal/Vertical down-scaling factor 0x0000_0000
VDDNSCF 0xFFF0_801C R/W Video Horizontal/Vertical down-scaling factor 0x0000_0000
LCD FIFO Control
FIFOCON 0xFFF0_8020 R/W FIFOs control 0x0000_0000
FIFOSTATUS 0xFFF0_8024 R FIFOs status 0x0000_0000
FIFO1PRM 0xFFF0_8028 R/W FIFO1 parameters 0x0000_0000
FIFO2PRM 0xFFF0_802C R/W FIFO2 parameters 0x0000_0000
FIFO1SADDR 0xFFF0_8030 R/W FIFO1 start address 0x0000_0000
FIFO2SADDR 0xFFF0_8034 R/W FIFO2 start address 0x0000_0000
FIFO1DREQCNT 0xFFF0_8038 R/W FIFO1 data request count 0x0000_0000
FIFO2DREQCNT 0xFFF0_803C R/W FIFO2 data request count 0x0000_0000
FIFO1CURADR 0xFFF0_8040 R FIFO1 current access address 0x0000_0000
FIFO2CURADR 0xFFF0_8044 R FIFO2 current access address 0x0000_0000
FIFO1RELACOLCNT 0xFFF0_8048 R/W FIFO1 real column count 0x0000_0000
FIFO2RELACOLCNT 0xFFF0_804C R/W FIFO2 real column count 0x0000_0000