Rainbow Electronics W90P710CDG - Manual (Page 41)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 41 - Revision B2
Table6.2.6 Half-word access read operation with Big Endian
ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
XD WIDTH WORD HALF WORD BYTE
Bit Number
CPU Reg Data
15 0
AB
15 0
CD
15 0
CD
15 0
DC
SA HAL HAU HA HA
Bit Number
SD
15 0
AB
15 0
CD
15 0
CD
15 0
DC
Bit Number
ED
15 0
AB
15 0
CD
15 0
CD
15 0
DX
15 0
DC
XA HAL HAL HA HA HA+1
SDQM [3-0] AAUU UUAA XXAA XXXA XXXA
Bit Number
XD
31 0
AB CD
31 0
AB CD
15 0
CD
7 0
D
7 0
C
Bit Number
Ext. Mem Data
31 0
ABCD 15 0
CD
7 0
D
7 0
C
Timing Sequence 1st read 2nd read
Table 6.2.7 and Table 6.2.8
Using big-endian and byte access, Program/Data path between register and external memory.
BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
BAL = Address whose LSB is 0,2,4,6,8,A,C,E
BAU = Address whose LSB is 1,3,5,7,9,B,D,F
BA0 = Address whose LSB is 0,4,8,C BA1 = Address whose LSB is 1,5,9,D
BA2 = Address whose LSB is 2,6,A,E BA3 = Address whose LSB is 3,7,B,F