Rainbow Electronics W90P710CDG - Manual (Page 139)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 139 - Revision B2
BITS DESCRIPTIONS
[31:25] Reserved -
[24] TxBErr
The Transmit Bus Error Interrupt high indicates the memory
controller replies ERROR response while EMC access system
memory through TxDMA during packet transmission process.
Reset EMC is recommended while TxBErr status is high.
If the TxBErr is high and EnTxBErr of MIEN register is enabled,
the TxINTR will be high. Write 1 to this bit clears the TxBErr
status.
1’b0: No ERROR response is received.
1’b1: ERROR response is received.
[23] TDU
The Transmit Descriptor Unavailable Interrupt high indicates
that there is no available Tx descriptor for packet transmission
and TxDMA will stay at Halt state. Once, the TxDMA enters the
Halt state, S/W must issues a write command to TSDR register to
make TxDMA leave Halt state while new Tx descriptor is
available.
If the TDU is high and EnTDU of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the TDU status.
1’b0: Tx descriptor is available.
1’b1: Tx descriptor is unavailable.
[22] LC
The Late Collision Interrupt high indicates the collision occurred in
the outside of 64 bytes collision window. This means after the 64
bytes of a frame has transmitted out to the network, the collision
still occurred. The late collision check will only be done while EMC
is operating on half-duplex mode.
If the LC is high and EnLC of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the LC status.
1’b0: No collision occurred in the outside of 64 bytes collision
window.
1’b1: Collision occurred in the outside of 64 bytes collision
window.