Rainbow Electronics W90P710CDG User Manual

Page 445

W90P710CD/W90P710CDG

Publication Release Date: September 19, 2006

- 445 -

Revision B2

Continued

BITS

DESCRIPTIONS

[1]

ETBREI

Enable Transmit Buffer Empty interrupt bit
An ETBREI means interrupt enable bit for TBR (Transmitter Buffer
Register) empty condition. An interrupt is issued when TBR is empty and
this bit is set to "1".
0 = TBR empty interrupt is disabled.
1 = TBR empty interrupt is enabled.

[0]

ERDRI

Enable Receive Data Ready interrupt bit
The active FIFO threshold level for this kind of interrupt when FIFO is
enabled is specified in RxTL1 and RxTL0 (bit 7 and bit 6 of SCFR at
base address + 8. Refer to description of SCFR for details). An
interrupt is issued if a data byte is ready for host to read when FIFO is
disabled or incoming data from card reaches active FIFO threshold level
when FIFO is enabled.

Interrupt Status Register (SCHI_ISR)

REGISTER

ADDRESS

R/W

DESCRIPTION

RESET VALUE

SCHI_ISR0

0xFFF8_5008 (DLAB = 0)

Interrupt Status Register 0

0x0000_00C1

SCHI_ISR1

0xFFF8_5808 (DLAB = 0)

Interrupt Status Register 1

0x0000_00C1

This register contains mainly interrupt status including transmission-related interrupts and SCPSNT

toggle interrupt. Transmission-related interrupt status is coded and prioritized as in UART
implementation. User may also find FIFO enable/disabled status reflecting what is set in bit 0 of SCFR
(write only Smart Card FIFO Register at base address + 8 when BDLAB = 0) and SCPSNT line status.

RESERVED

SCPSNT

SCPTI INTS2 INTS1 INTS0

Interrupt

pending