Rainbow Electronics W90P710CDG - Manual (Page 241)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 241 - Revision B2
BITS DESCRIPTIONS
[31:7] Reserved -
[6] ERRIEN
Bus Error Interrupt Enable
[5] DRdIEN
DMA Read Interrupt Enable
This bit controls the SD host controller interrupt generation from the
interrupt of the DMA read operation.
1’b0: DMA read interrupt is masked from SD host controller interrupt
generation
1’b1: DMA read interrupt can participate in SD host controller interrupt
generation
[4]
DWrIEN
DMA Write Interrupt Enable
This bit controls the SD host controller interrupt generation from the
interrupt of the DMA write operation.
1’b0: DMA write interrupt is masked from SD host controller interrupt
generation
1’b1: DMA write interrupt can participate in SD host controller interrupt
generation
[3]
SDHIIEN
Secure Digital Host Controller Interface Interrupt Enable
This bit controls the SD host controller interrupt generation from the
interrupt of Secure Digital host controller.
1’b0: Secure Digital host controller’s interrupt is masked from SD host
controller interrupt generation
1’b1: Secure Digital host controller’s interrupt can participate in SD host
controller interrupt generation
[0] SDGIEN
SD Host Global Interrupt Enable
This bit controls the interrupt generation of SD host controller Globally.
1’b0: Disable SDI host controller interrupt generation globally
1’b1: Enable SD host controller interrupt generation globally