Rainbow Electronics W90P710CDG - Manual (Page 43)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 43 - Revision B2
Table 6.2.9 and Table 6.2.10
Using little-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0,4,8,C X = Don’t care
nWBE [3-0] / SDQM [3-0] = A means active and U means inactive
Table6.2.9 Word access write operation with little Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
31 0
ABCD 31 0
ABCD 31 0
ABCD
SA WA WA WA
Bit Number
SD
31 0
ABCD 31 0
AB CD 31 0
A B C D
Bit Number
ED
31 0
ABCD 15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
XA WA WA WA+2 WA WA+1 WA+2 WA+3
nWBE [3-0] /
SDQM [3-0]
AAAA XXAA XXAA XXXA XXXA XXXA XXXA
Bit Number
XD
31 0
ABCD 15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Bit Number
Ext. Mem Data
31 0
ABCD 15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Timing Sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write
Table6.2.10 Word access read operation with Little Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
31 0
ABCD 31 0
ABCD 31 0
ABCD
SA WA WA WA
Bit Number
SD
31 0
ABCD 31 0
AB CD 31 0
A B C D
Bit Number
ED
31 0
ABCD 31 0
XX CD 31 0
AB CD 31 0
X X X D
31 0
X X C D
31 0
X B C D
31 0
A B C D
XA WA WA WA+2 WA WA+1 WA+2 WA+3
SDQM [3-0] AAAA XXAA XXAA XXXA XXXA XXXA XXXA
Bit Number
XD
31 0
ABCD 15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Bit Number
Ext. Mem Data
31 0
ABCD 15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Timing Sequence 1st read 2nd read 1st read 2nd read 3rd read 4th read