FUJITSU MB91F109 FR30 - Manual (Page 66)

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CHAPTER 2 CPU
2.4 Data Structure
FR-series data is mapped as follows:
• Bit ordering: Little endian
• Byte ordering: Big endian
■ Bit Ordering
The FR series uses little endian for bit ordering.
Figure 2.4.1 shows data mapping in bit ordering mode.
Figure 2.4-1 Data Mapping in Bit Ordering Mode
■ Byte Ordering
The FR series uses big endian for byte ordering.
Figure 2.4.2 shows data mapping in byte ordering mode.
Figure 2.4-2 Data Mapping in Byte Ordering Mode
bit 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
MSB LSB
MSB LSB
bit31 23 15 7 0
10101010 11001100 11111111 00010001
bit
7
0
10101010
11001100
11111111
00010001
Memory
Address n
Address (n+1)
Address (n+2)
Address (n+3)