FUJITSU MB91F109 FR30 - Manual (Page 104)

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CHAPTER 3 CLOCK GENERATOR AND CONTROLLER
3.4 DMA Request Suppression Register (PDRR)
The DMA request suppression register (PDRR) is used to temporarily suppress DMA
requests to lighten the load to the CPU.
■ Configuration of the DMA Request Suppression Register (PDRR)
The configuration of the DMA request suppression register (PDRR) is shown below:
■ Bit Functions of the DMA Request Suppression Register (PDRR)
[bit 11 to bit 08] D3 to D0
Writing a value other than 0 to this register suppresses any subsequent DMA transfer
requests to the CPU. Thereafter, DMA transfer is disabled unless the register is set to 0.
15 14 13 12 11 10 09 08
00000482
H
D3 D2 D1 D0 ----0000 R/W
Initial value Access