FUJITSU MB91F109 FR30 - Manual (Page 251)

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8.2 Interrupt Controller Block Diagram
8.2 Interrupt Controller Block Diagram
Figure 8.2-1 is an interrupt controller block diagram.
■ Interrupt Controller Block Diagram
Figure 8.2-1 Block Diagram of the Interrupt Controller
INTO
OR
5
NMI / LEVEL4 to 0
4
HLDCAN
ICR00
RI00 6
/
VCT5 to 0
ICR47
RI47
(DLYIRQ) DLYI
*1
*2
*3
R-BUS
NMI
processing
VECTOR check
LEVEL and VECTOR
generation
HLDREQ
cancel
request
*1: DLYI is the delayed interrupt module (See Chapter 7, "Delayed Interrupt Module," for more information.)
*2: INT0 is a wakeup signal for the clock controller in sleep or stop state.
*3: HLDCAN is a bus yield request signal to a bus master other than the CPU.
Priority check
LEVEL check