FUJITSU MB91F109 FR30 - Manual (Page 221)

197
4.19 Program Example for External Bus Operation
stb r0,@r1 Write to dscr register
init_amd0 ldi:8 #0x08,r0 // 16-bit bus, 0-wait
ldi:20 #0x620,r1 // amd0 register address setting
stb r0,@r1 // Write to amd0 register
init_amd1 ldi:8 #0x0a,r0 // 16-bit bus, 2-wait
ldi:20 #0x621,r1 // amd1 register address setting
stb r0,@r1 // Write to amd1 register
init_amd32 ldi:8 #0x49,r0 // Usual, 16-bit bus, 1-wait
ldi:20 #0x622,r1 // amd32 register address setting
stb r0,@r1 // Write to amd32 register
init_amd4 ldi:8 #0x88,r0 // DRAM, 16-bit bus
ldi:20 #0x623,r1 // amd4 register address setting
stb r0,@r1 // Write to amd4 register
init_amd5 ldi:8 #0x88,r0 // DRAM, 16-bit bus
ldi:20 #0x624,r1 // amd5 register address setting
stb r0,@r1 // Write to amd5 register
init_dmcr4 ldi:20 #0x0c90,r0 //
// page size=256,Q1/Q4-wait,Page
1CAS-2WE, CBR, without parity
ldi:20 #0x62c,r1 // dmcr4 register address setting
sth r0,@r1 // Write to dmcr4 register
init_dmcr5 ldi:20 #0x10c0,r0 //
// page size=512, without Q1/Q4-wait,
Page
2CAS-1WE, CBR, without parity
ldi:20 #0x62e,r1 // dmcr5 register address setting
sth r0,@r1 // Write to dmcr5 register
init_rfcr ldi:20 #0x0205,r0 // REL=2, without R1W/R3W-wait,
refresh, 1/8