FUJITSU MB91F109 FR30 - Manual (Page 252)

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CHAPTER 8 INTERRUPT CONTROLLER
8.3 Interrupt Control Register (ICR)
One interrupt control register is provided for each type of interrupt input and is used to
set the interrupt level of the corresponding interrupt request.
■ Configuration of Interrupt Control Register (ICR)
The configuration of the interrupt control register (ICR) is shown below:
■ Bit Functions of Interrupt Control Register (ICR)
[bit 4 to 0] ICR 4 to 0
These are the interrupt level setting bits that are used to specify the interrupt level of the
corresponding interrupt request.
When the interrupt level specified by this register equals or exceeds the level mask value set
in the CPU ILM register, the CPU masks the interrupt request.
When the register is reset, the bits are initialized to 11111
B
.
Table 8.3-1 summarizes the correspondence between the interrupt level setting bits and the
interrupt levels.
bit7
6 5 4 3 2 1 0
ICR4 ICR3 ICR2 ICR1 ICR0 ---11111
R R/W R/W R/W R/W
(Initial value)