FUJITSU MB91F109 FR30 - Manual (Page 368)

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CHAPTER 15 DMAC
❍ Required pin input mode: edge, descriptor address: external
❍ Required pin input mode: edge, descriptor address: internal
The section from when a DREQn is generated to when the DMAC operation starts shows the
case where the DMAC operation starts first.
The DMAC operation may be delayed because the CPU fetches instructions and accesses
data, thereby creating bus contention.
(A)
CLK
DREQn
RDXD
WRnX
#2H
#2H
S
S
#1H
#1L #1H
#1L #0L #0H
#0L #0H #2L
#2L
Data pin
Addr pin
DACK
EOP
(A)
CLK
DREQn
RDXD
WRnX
DACK
EOP
S
S
Addr pin
Data pin