FUJITSU MB91F109 FR30 - Manual (Page 238)

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CHAPTER 6 EXTERNAL INTERRUPT/NMI CONTROLLER
6.3 External Interrupt Request Register (EIRR)
When the external interrupt request register (EIRR) is read, it indicates that there are
external interrupt requests. When it is written, the flip-flops indicating these requests
are cleared.
■ External Interrupt Request Register (EIRR)
The configuration of the external interrupt request register (EIRR) is shown below:
When the external interrupt request register (EIRR) is read, it indicates that there are external
interrupt requests. When it is written, the flip-flops indicating these requests are cleared.
If a bit of the register is "1" when it is read, it indicates that the corresponding pin has an
external interrupt request.
Writing "0" to a bit of the register clears the flip-flop of the interrupt request corresponding to the
bit. Writing "1" to the register is ignored.
When the register is read in read-modify-write mode, "1" is always read.
Users cannot read or write the NMI flag.
15 14 13 12 11 10 9 8
EIRR
Address:000094
H
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00000000 R/W
Access Initial value