FUJITSU MB91F109 FR30 - Manual (Page 309)

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12.2 Control Status Register (TMCSR)
[bit 3] INTE
This is an interrupt enable bit. When the UF bit changes to "1" while this bit is "1", an
interrupt request is issued. No interrupt request is issued while this bit is "0".
[bit 2] UF
This is a timer interrupt request flag, which is set to "1" when the counter value underflows
0000
H
to FFFF
H
. Setting the bit to "0" clears the flag.
Setting the bit to "1" has no effect.
A Read Modify Write instruction reads "1" from this bit.
[bit 1] CNTE
This is a timer count enable bit. Setting this bit to "1" makes the timer wait for a start trigger
signal. Setting the bit to "0" stops the counter.
[bit 0] TRG
This is a software trigger bit. Setting the bit to "1" activates the software trigger, which loads
the value in the reload register to the counter to start counting.
Setting the bit to "0" has no effect. A read instruction always reads "0" from this bit.
The trigger input by this register works only when CNTE is "1". Nothing occurs when CNTE
is "0".