FUJITSU MB91F109 FR30 - Manual (Page 254)

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CHAPTER 8 INTERRUPT CONTROLLER
8.4 Hold Request Cancel Request Level Setting Register
(HRCL)
The HRCL register is used to set the interrupt level for issuing a hold request cancel
request.
■ Configuration of Hold Request Cancel Request Level Setting Register (HRCL)
The register configuration of the hold request cancel request/level setting register (HRCL) is as
follows:
■ Bit Functions of Hold Request Cancel Request Level Setting Register (HRCL)
[bit4 to 0] LVL4 to 0
These bits specify the interrupt level for issuing a hold request cancel request to the bus
master.
When an interrupt request having a level higher than the interrupt level set in this register is
generated, a hold request cancel request is issued to the bus master.
The LVL4 bit is fixed to "1" and cannot be set to "0".
bit7
6 5 4 3 2 1 0
00000431
H
LVL4 LVL3 LVL2 LVL1 LVL0 ---11111
R R/W R/W R/W R/W
Address
(Initial value)