FUJITSU MB91F109 FR30 - Manual (Page 453)

429
INDEX
external trigger or internal timer to start A/D converter,
using .......................................................... 280
external wait cycle timing chart ............................ 172
F
FBGA-112, outside dimension ................................. 9
FBGA-112, pin arrangement .................................. 12
first word of descriptor.......................................... 332
flag and interrupt occurrence ............................... 260
flash memory register .......................................... 352
flash memory status register (FSTR) ................... 355
flash memory, block diagram of ........................... 354
flash memory, outline of ....................................... 352
flash memory, sector configuration of .................. 357
FR-CPU ................................................................... 2
FR-CPU programming mode (16 bits, read/write) 359
FR-CPU ROM mode (32 bits, read only) ............. 359
frequency combination depending on clock doubler
function, operating ..................................... 106
FR-series instruction ............................................ 409
G
gear control register (GCR), bit function of ............ 82
gear control register (GCR), configuration of ......... 82
gear controller block diagram................................. 87
gear function setting............................................... 87
general control register 1 (GCN1), bit function of 312
general control register 1 (GCN1),
configuration of .......................................... 311
general control register 2 (GCN2)........................ 314
general-purpose register.................................. 33, 35
H
half-word access .................................. 141, 148, 152
hardware configuration ........................................ 236
hardware sequence flag....................................... 364
Harvard-Princeton bus converter ........................... 32
high coding efficiency............................................. 30
high-speed page mode, DRAM interface timing
chart in ....................................................... 182
hold request cancel request level setting register
(HRCL), bit function of ............................... 230
hold request cancel request level setting register
(HRCL), configuration of ............................ 230
hold request cancel request sequence ................ 237
hold request cancel request, criteria for
determining ................................................ 235
hold request cancel request, interrupt level for .... 235
HRCL register ...................................................... 339
hyper DRAM interface read timing chart ..............188
hyper DRAM write timing chart.............................189
hyper DRAM interface timing chart.......................190
I
I flag........................................................................55
I/O circuit format .....................................................22
I/O map.................................................................371
I/O map, how to read ............................................370
I/O port register.....................................................202
I/O port, basic block diagram of............................202
immediate value setting or 16/31-bit immediate value
transfer .......................................................413
initial value, allocating variable with......................396
initial vector table area............................................44
initialization ...........................................................258
initialization by power-on reset ...............................28
initialization by resetting .........................................68
input of external reset signal...................................26
input of source oscillation at power-on ...................27
input pin, treatment of unused ................................26
instruction format ..................................................407
instruction overview ................................................46
instruction type .....................................................407
instruction, how to read ........................................403
INT instruction, operation for ..................................65
INTE instruction, operation for................................65
interchannel priority order.....................................339
internal architecture ................................................31
internal clock operation.........................................287
internal memory, external transfer from................341
internal timer.........................................................255
internal timer or external trigger to start
A/D converter, using ...................................280
interregister transfer instruction ............................414
interrupt ................................................................319
interrupt cause, clearing .......................................233
interrupt control.....................................................353
interrupt control register (ICR) mapping .................56
interrupt control register (ICR), bit function of.56, 228
interrupt control register (ICR),
configuration of .....................................56, 228
interrupt controller.....................................................4
interrupt controller block diagram .........................227
interrupt controller hardware configuration ...........224
interrupt controller register....................................225
interrupt controller, major function ........................224
interrupt flag set timing for data reception in
mode 0 .......................................................260