FUJITSU MB91F109 FR30 - Manual (Page 283)

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10.8 CLK Synchronous Mode
• SCR register
• PEN: 0
• P, SBL, A/D: These bits are invalid.
• CL: 1
• REC: 0 (for initialization)
• RXE, TXE: At least one must be set to 1.
• SSR register
• 1 for using interrupts or 0 for using no interrupt
• TIE: 0
❍ Start of communication
Writing to the SODR register starts communication. Dummy transmission data must be written
to the SODR register, even for reception only.
❍ End of communication
The end of communication can be detected by the fact that the RDRF flag of the SSR register
changes to "1". Check the ORE bit of the SSR register to determine whether communication
has been successful.