FUJITSU MB91F109 FR30 - Manual (Page 109)

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3.7 Watchdog Timer Reset Delay Register (WPR)
3.7 Watchdog Timer Reset Delay Register (WPR)
The watchdog timer reset delay register (WPR) clears the flip-flop for the watchdog
timer. This register can be used to delay watchdog timer resets.
■ Configuration of Watchdog Timer Reset Delay Register (WPR)
The configuration of the watchdog timer reset delay register (WPR) is shown below:
■ Bit Functions of Watchdog Timer Reset Delay Register (WPR)
Bits 07 to 00 (D7 to D0)
When A5
H
and 5A
H
are written successively to this register, the flip-flop for the watchdog
timer is cleared to 0 immediately after 5A
H
is written to delay the watchdog timer reset.
The value read from this register is undefined. There are no restrictions on the time between
A5
H
and 5A
H
, but the watchdog timer is reset if the writing of both data items is not finished
within the time shown in Table 3.7.1. Because the flip-flop is automatically cleared during
the stop, sleep, or hold state, the watchdog timer reset is delayed automatically when these
conditions occur.
φ
is twice as large as X0 when GCR CHC is 1, and becomes the PLL oscillation frequency
when CHC is 0.
07 06 05 04 03 02 01 00
00000485
H
D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXX W
Initial value Access
Table 3.7-1 Watchdog Timer Cycles Specified by WT1 and WT0
WT1 WT0 Minimum WPR write interval
required to suppress the
watchdog timer reset
Time from last 5AH writing to WPR
to watchdog timer reset
0 0
φ ×
2
15 φ ×
2
15
to
φ ×
2
16
0 1
φ ×
2
17 φ ×
2
17
to
φ ×
2
18
1 0
φ ×
2
19 φ ×
2
19
to
φ ×
2
20
1 1
φ ×
2
21 φ ×
2
21
to
φ Ч
2
22