FUJITSU MB91F109 FR30 - Manual (Page 452)

428
INDEX
descriptor, first word of ......................................... 332
descriptor, second word of ................................... 334
descriptor, third word of........................................ 334
detection data register 0 (BSD0) .......................... 293
detection data register 1 (BSD1) .......................... 293
detection of error not found .................................. 401
detection result register (BSRR)........................... 294
detection, 0........................................................... 295
detection, 1........................................................... 295
detection, change-point ........................................ 296
device handling ...................................................... 26
DICR DLYI bit....................................................... 222
direct addressing .................................................... 47
direct addressing area...................................... 25, 44
direct addressing instruction ................................ 422
DMA controller DMAC .............................................. 3
DMA request suppression register (PDRR), bit
function of .................................................... 80
DMA request suppression register (PDRR),
configuration of ............................................ 80
DMA suppression circuit block diagram ............... 103
DMA suppression, setting for ............................... 103
DMA transfer for interrupt with higher priority,
suppression of............................................ 339
DMA transfer request, using resource interrupt
request as a ............................................... 339
DMAC block diagram ........................................... 325
DMAC characteristic............................................. 324
DMAC control status register (DACSR),
bit function of.............................................. 327
DMAC control status register (DACSR),
configuration of .......................................... 327
DMAC internal register, transfer to....................... 340
DMAC parameter descripter pointer (DPDP) ....... 326
DMAC pin control register (DATCR),
bit function of.............................................. 330
DMAC pin control register (DATCR),
configuration of .......................................... 329
DMAC register...................................................... 324
DMAC transfer operation in sleep mode .............. 340
double type and long double type, using.............. 397
DRAM control pin ................................................. 155
DRAM control register 4/5 (DMCR4/5),
bit function of.............................................. 127
DRAM control register 4/5 (DMCR4/5),
configuration of .......................................... 127
DRAM device, connection example of ................. 158
DRAM interface ........................................ 3, 116, 159
DRAM interface timing chart in high-speed
page mode ................................................. 182
DRAM interface, hyper......................................... 160
DRAM interface, single ........................................ 160
DRAM interface, usual ......................................... 160
DRAM refresh ...................................................... 161
DRAM signal control register (DSCR),
bit function of ............................................. 136
DRAM signal control register (DSCR),
configuration of .......................................... 136
E
EIT cause............................................................... 52
EIT characteristic ................................................... 52
EIT event acceptance, priority for .......................... 62
EIT vector table...................................................... 60
EIT, note on ........................................................... 53
EIT, return from...................................................... 52
emulator and monitor debuggers ......................... 402
enable interrupt request register (ENIR) .............. 213
enhanced I/O operation instruction ........................ 30
enhanced interrupt processing function ................. 30
erase chip ............................................................ 362
error not detected................................................. 401
execution status of automatic algorithm............... 353
external bus access ............................................. 143
external bus operation, program example for ...... 196
external bus operation, program specification
example for ................................................ 196
external bus request ............................................ 161
external clock ....................................................... 256
external clock, not on using an .............................. 26
external interrupt operation .................................. 216
external interrupt operation procedure................. 216
external interrupt request level............................. 217
external interrupt request register (EIRR) ............ 214
external interrupt/NMI controller block diagram ... 212
external interrupt/NMI controller register.............. 212
external level register (ELVR) .............................. 215
external pin control register 0 (EPCR0),
bit function of ............................................. 132
external pin control register 0 (EPCR0),
configuration of .......................................... 132
external pin control register 1 (EPCR1),
bit function of ............................................. 135
external pin control register 1 (EPCR1),
configuration of .......................................... 135
external pin function (I/O port or control pin),
selection of................................................. 205
external reset pin or software reset, releasing from68
external reset signal, input of ................................. 26
external transfer from internal memory ................ 341