FUJITSU MB91F109 FR30 - Manual (Page 359)

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15.6 DMAC Transfer Modes
15.6 DMAC Transfer Modes
The DMAC supports the following three transfer modes:
This section explains the operation in these modes.
• Single/block transfer mode
• Continuous transfer mode
• Burst transfer mode
■ Single/Block Transfer Mode
1. The initialization routine sets the descriptor.
2. The program initializes the DMA transfer request source. To use the internal peripheral
circuit as the transfer request source, enable interrupt requests and disable interrupts in the
ICR of the interrupt controller.
3. The program sets the target DOEn bit of the DACSR to 1.
--- This completes the setting for DMA. ---
4. Upon detection of a DMA transfer request input, the DMAC requests bus control right from
the CPU.
5. When the bus control right is transferred from the CPU, the DMAC accesses three words of
information of the descriptor through the bus.
6. While decrementing DMACT, the DMAC performs a transfer based on the information stored
in the descriptor as many times as specified by BLK or until DMACT reaches 0. The DMAC
outputs a transfer request acknowledgment signal during data transfer (if external transfer
request input is used). When decremented DMACT reaches 0, the DMAC outputs a transfer
end signal during data transfer.
7. The DMAC clears the transfer request input.
8. The DMAC increments or decrements SADR or DADR and writes the result together with the
DMACT value back to the descriptor.
9. The DMAC returns the bus control right to the CPU.
10.If the DMACT value is 0, the DMAC sets DACSR DEDn to 1 and causes an interrupt to the
CPU if interrupts have been enabled.
The number of minimum required cycles per transfer is shown below (on the assumption that
the descriptor is stored in built-in RAM, data is transferred between external busses, and the
data length is counted in bytes):
• When both transfer source and destination addresses are fixed: (6 + 5 × BLK) cycles
• When one of the transfer source and destination addresses is fixed: (7 + 5 × BLK) cycles
• When both transfer source and destination addresses are incremented or decremented: (8+
5 × BLK) cycles