FUJITSU MB91F109 FR30 - Manual (Page 276)

252
CHAPTER 10 UART
10.4 Serial Input Data Register (SIDR) and Serial Output Data
Register (SODR)
The serial input data register (SIDR) is a data buffer register for receiving data, and the
serial output data register (SODR) is a data buffer register for transmitting data.
When 7-bit data is used, bit 7 (D7) is invalid. Write to the SODR register when TDRE of
the SSR register is "1".
■ Configuration of Serial Input Data Register (SIDR) and Serial Output Data Register (SODR)
The configuration of the serial input data register (SIDR) and serial output data register (SODR)
is shown below:
An instruction to write to the above address means to write to the SODR register, and an
instruction to read from the above address means to read the SIDR register.
7 6 5 4 3 2 1 0
SIDR 00001D
H
Address: 000021
H
D7 D6 D5 D4 D3 D2 D1 D0
000025
H
R R R R R R R R
7 6 5 4 3 2 1 0
SODR
D7 D6 D5 D4 D3 D2 D1 D0
W W W W W W W W
Initial value
Undefined
Undefined Address: same as above