FUJITSU MB91F109 FR30 - Manual (Page 30)

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CHAPTER 1 OVERVIEW
1.2 General Block Diagram of MB91F109
Figure 1.2.1 is a general MB91F109 block diagram.
■ General Block Diagram of MB91F109
Figure 1.2-1 General Block Diagram of MB91F109
Notes:
• Terminals are represented by the function (some terminals are actually multiplexed).
• When REALOS is used, perform time management using an external interrupt or internal
timer.
I-bus(16bit)
C-bus
(32bit)
RAS0 RAS1
CS0L CS1L
EOP0 EOP1 EOP2
16bit
FLASH ROM
254KB
RSTX
INT0-INT3
NMIX
AN0-AN3
AVCC AVRH
D31-D16
A24-A00
RDX
WR0X-1X
D-bus(32bit) RDY
CLK
BRQ BGRNTX
CS0X-5X
DREQ0 DREQ1 DREQ2
DACK0 DACK1 DACK2
32bit
CS0H CS1H
DW0X DW1X
X0 X1
R-bus
(16bit)
SC0 SC1 SC2
SO0 SO1 SO2
with Baud Rate Timer AVSS AVRL
SI0 SI1 SI2
UART (3ch) 10bit A/D Converter
(4ch)
PWM Timer (4ch) Reload Timer
(3 ch)
Port
ATGX
OCPA0-OCPA3
TRG0-3
RAM 2KB
Port 0-B
DRAM Controller
Bus Controller
Bus Converter
Bus Converter
Interrupt Control Unit
Clock Control Unit
(Watch Dog Timer)
DMAC (8ch)
Bit Search Module
RAM 2KB
FR CPU
Harvard
Princeton