10 usual dram read cycles – FUJITSU MB91F109 FR30 User Manual

Page 201

background image

177

4.17 Bus Timing

4.17.10 Usual DRAM Read Cycles

This section provides usual DRAM read cycle timing charts.

■

Usual DRAM Read Cycle Timing Charts

❍

Bus width: 16 bits, access: half-words

Figure 4.17-18 Example 1 of Usual DRAM Read Cycle Timing Chart

Q1

Q2

Q3

Q4

Q5

CLK

A24-00

X

#0 row.adr.

#0 col.adr

D31-24

#0

D23-16

#1

RAS
CAS
WEL
WEH

A24-00

X

#0 row.adr.

#0 col.adr

D31-24

#0

D23-16

#1

RAS
CASL
CASH
WE

1CAS/2WE

1)

2CAS/1WE

2)