FUJITSU MB91F109 FR30 - Manual (Page 456)

432
INDEX
standby mode (stop or sleep state),
returning from............................................. 234
standby mode state transition ................................ 98
standby mode, type of operation in ........................ 90
starting multiple PWM timer channel using 16-bit
reload timer ................................................ 322
starting multiple PWM timer channel via software 321
step-trace-trap ........................................................ 50
step-trace-trap, operation for.................................. 66
stop controller block diagram ................................. 92
stop erase, temporary .......................................... 363
stop or sleep state, mapping address of program
used to put system into ................................ 91
stop state, outline of ............................................... 90
stop state, returning from ............................... 93, 216
stop state, transition to ........................................... 92
structure assigning ............................................... 396
suppression of DMA transfer for interrupt with higher
priority ........................................................ 339
system condition code register (SCR).................... 40
system stack pointer (SSP) .............................. 37, 57
T
table base register (TBR) ................................. 37, 59
TBR ........................................................................ 37
temporary sector erase stop status ...................... 366
temporary stop erase ........................................... 363
term used in pin status list, explanation of ........... 383
third word of descriptor......................................... 334
timebase timer...................................................... 100
timebase timer clear register (CTBR),
bit function of................................................ 81
timebase timer clear register (CTBR),
configuration of ............................................ 81
timing chart, automatic wait cycle......................... 171
timing chart, basic read cycle ............................... 162
timing chart, basic write cycle............................... 164
timing chart, code used in .................................... 342
timing chart, external wait cycle ........................... 172
timing chart, hyper DRAM interface ..................... 190
timing chart, read and write combination cycle .... 170
timing chart, read cycle ........................................ 166
timing chart, single DRAM interface ..................... 187
timing chart, usual DRAM interface read.............. 173
timing chart, usual DRAM interface write ............ 175
timing chart, usual DRAM read cycle ................... 177
timing chart, usual DRAM write cycle................... 179
timing chart, write cycle ........................................ 168
TMCSR ................................................................ 284
transfer end signal, output of ............................... 338
transfer mode, burst............................................. 337
transfer mode, continuous ................................... 336
transfer mode, single/block .................................. 335
transfer request acknowledgment signal,
output of..................................................... 338
transfer stop in continuous transfer mode for 16/8-bit
data (both address are changed)............... 348
transfer stop in continuous transfer mode for 16/8-bit
data (either address is unchanged) ........... 347
transfer termination (both address are changed). 350
transfer termination (either address is
unchanged)................................................ 349
transfer to DMC internal register.......................... 340
transition to sleep state .......................................... 95
transition to stop state............................................ 92
transition to stop state using intruction................... 92
transmit operation ................................................ 257
treatment of NC pin................................................ 27
treatment of unused input pin ................................ 26
U
UART ....................................................................... 3
UART block diagram............................................ 247
UART characteristic ............................................. 246
UART clock selection........................................... 255
UART operation mode ......................................... 255
UART register ...................................................... 246
UART, example for use of.................................... 263
UART, note on using............................................ 263
undefined-instruction exception, operation for ....... 66
underflow operation ............................................. 287
user interrupt/NMI, operation for ............................ 64
user stack pointer (USP)........................................ 37
USP........................................................................ 37
usual DRAM interface read timing chart .............. 173
usual DRAM interface write timing chart............. 175
usual DRAM read cycle timing chart.................... 177
usual DRAM write cycle timing chart ................... 179
U-TIMER (UTIM).................................................. 241
U-TIMER block diagram....................................... 240
U-TIMER control register (UTIMC) ...................... 241
U-TIMER register ................................................. 240
UTIMIC................................................................. 241
UTIMR.................................................................. 241
V
variable allocation with initial value ...................... 396