FUJITSU MB91F109 FR30 - Manual (Page 355)

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15.4 DMAC Pin Control Register (DATCR)
[bit 16, 8, 0] EPDEn
These bits specifies the time when the transfer end output signal is to be generated from the
corresponding output pin and also specify whether to enable the output function of the
corresponding transfer end output signal pin.
These bits are initialized to "00" by resetting.
The bits can be both read and written.
Table 15.4-3 Specification of Transfer End Output
EPSEn EPDEn Operation control function
0 0 Disables transfer end output.
0 1 Enables transfer end output. Transfer end is output when
transfer destination data is accessed.
1 0 Transfer completion output enabled; output when accessing
the transfer source data access
1 1 Enables transfer end output. Transfer end is output when
transfer source and destination data is accessed.