FUJITSU MB91F109 FR30 - Manual (Page 454)

430
INDEX
interrupt flag set timing for data reception in
mode 1 ....................................................... 261
interrupt flag set timing for data reception in
mode 2 ....................................................... 261
interrupt flag set timing for data tranmission in mode
0, 1 or 2 ...................................................... 262
interrupt level.......................................................... 54
interrupt level mask register (ILM).................... 41, 55
interrupt number ................................................... 222
interrupt occurrence and flag ............................... 260
interrupt stack......................................................... 58
interrupt vector ..................................................... 379
interrupt with higher priority, suppression DMA
transfer for.................................................. 339
interrupt, return by way of ................................ 93, 96
interrupt/NMI .......................................................... 50
interrupt/NMI, level mask for .................................. 55
interval timer, other .................................................. 4
K
-K lib option specifying when using character string
manipulation function ................................. 397
L
L or H output from PWM timer.............................. 320
latchup prevention .................................................. 26
level mask for interrupt/NMI ................................... 55
linear 4-gigabyte memory space ............................ 30
little endian area, allocating stack to .................... 398
little endian register (LER), bit function of ............ 138
little endian register (LER), configuration of ......... 138
little endian, outline of .......................................... 147
load and store ........................................................ 46
logical operation and bit manipulation .................... 47
logical operation instruction.................................. 411
low power consumption.......................................... 30
LQFP-100, outside dimension.................................. 8
LQFP-100, pin arrangement .................................. 11
M
manipulating data other than character array with
character string munipulation function ....... 397
mapping address of program used to put system into
stop or sleep state........................................ 91
MB91F109 memory map........................................ 44
MB91F109, general block diagram of ...................... 6
MDH/MDL .............................................................. 37
memory load instruction ....................................... 413
memory map .......................................................... 24
memory map commen to FR series....................... 45
memory store instruction...................................... 414
mode code addressing......................................... 405
mode data .............................................................. 70
mode pin ................................................................ 69
mode pin (MD0 to MD2)......................................... 27
mode register (MODR)........................................... 70
mode register (MODR), note on writing to ............. 70
multiple PWM timer channel using 16-bit reload timer,
starting ....................................................... 322
multiple PWM timer channel via software,
starting ....................................................... 321
multiplication and division instruction................... 412
multiplication/division result register (MDH/MDL) .. 37
N
NC pin, treatment of............................................... 27
NMI ...................................................................... 233
NMI operation ...................................................... 218
nonmaskable interrupt (NMI) ............................... 233
nstruction that can be placed in delay slot ............. 50
O
o-detection data register (BSD0) ......................... 293
one-shot operation ............................................... 317
operation mode ...................................................... 69
other instruction ................................................... 417
outside dimension, FBGA-112 ................................. 9
outside dimension, LQFP-100 ................................. 8
outside dimension, QFP-100 ................................... 7
P
peripheral clock, block that uses............................ 89
pin arrangement, FBGA-112.................................. 12
pin arrangement, LQFP-100 .................................. 11
pin arrangement, QFP-100 .................................... 10
pin condition at power-on....................................... 27
pin function............................................................. 14
pin status for each CPU status ............................ 384
pin status list, term used in .................................. 383
PLL clock setting, example of .............................. 108
PLL control register (PCTR), bit function of ........... 86
PLL control register (PCTR), configuration of ........ 86
port data register (PDR), configuration of ............ 203
postponing resetting............................................... 99
power pins (Vcc and Vss), connection of............... 27
power save mode..................................................... 4
power-on reset, initialization by.............................. 28
power-on, at ........................................................... 27