FUJITSU MB91F109 FR30 User Manual

Page 108

CHAPTER 3 CLOCK GENERATOR AND CONTROLLER

When the clock doubler is set to ON, the CPU gear is fixed regardless of the GCR value and
therefore the gear can also be set directly to the desired value.

[Example of programming]

[bit 09] Reserved bit

Always write 1 to this bit.

[bit 08] CHC

This bit selects the source of the reference clock. This bit is initialized by resetting. While
the VSTP bit of the PCTR register is 1, an attempt to write 0 to this bit is ignored.

When the system shifts to stop mode while the VSTP bit of the PCTR is 0, PLL stops oscillation
but VSTP remains 0. When the system returns from the stop mode because of an external
interrupt, about 100 microseconds are required in addition to the oscillation stabilization wait
time set in STCR OSC1 and OSC0 before PLL oscillation stabilizes. Therefore, do not set this
bit to 0 before that.

See Section 3.10.1, "Stop state," for the procedure on returning from the stop mode and internal
operation.

ldi

#0×484,

ldi

#0×0d,

stb

r0,

@r1

; CPU:1/1, Peripheral:1/8

ldi

#0×484,

ldi

#0×cd,

stb

r0,

@r1

; CPU:1/8, Peripheral:1/8

Temporarily set to the same ratio

ldi

#0×c5,

stb

r0,

@r1

; CPU:1/8, Peripheral:

Set to the desired ratio

CHC

Clock source

Using two divisions of the oscillation circuit as the reference clock (initial value)

Using the oscillation output from PLL as the reference clock