FUJITSU MB91F109 FR30 - Manual (Page 166)

142
CHAPTER 4 BUS INTERFACE
❍ Byte access (during execution of LDUB and STB instructions)
Figure 4.16-5 Relationship between Internal Register and External Data Bus for Byte Access
■ Data Bus Width
The following shows the relationship between the internal register and external data bus for
each data bus width.
❍ 16-bit bus width
Figure 4.16-6 Relationship between Internal Register and External Data Bus for 16-bit Bus Width
AA
AA
AA AA
D31
D23
D15
D07
D31
D23
D31
D23
D15
D07
D31
D23
(a) Lower bits of output address "0"
Internal register Internal register External bus External bus
(b) Lower bits of output address "1"
"00" "10"
AA Read/Write AA CC
BB BB DD
CC
DD
D31
D23
D15
D07
D31
D23
Internal register External bus
Lower part of the output address