2 port data register (pdr) – FUJITSU MB91F109 FR30 User Manual
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5.2 Port Data Register (PDR)
5.2
Port Data Register (PDR)
The port data registers (PDR2 to PDRF) are I/O port I/O data registers. The
corresponding data direction registers (DDR2 to DDRF) perform I/O control.
■
Configuration of Port Data Register (PDR)
The port data register (PDR) is configured as follows:
7
6
5
4
3
2
1
0
PDR2
Address: 000001
H
P27
P26
P25
P24
P23
P22
P21
P20
XXXXXXXX
B
R/W
7
6
5
4
3
2
1
0
PDR3
Address: 000000
H
P37
P36
P35
P34
P33
P32
P31
P30
XXXXXXXX
B
R/W
7
6
5
4
3
2
1
0
PDR4
Address: 000007
H
P47
P46
P45
P44
P43
P42
P41
P40
XXXXXXXX
B
R/W
7
6
5
4
3
2
1
0
PDR5
Address: 000006
H
P57
P56
P55
P54
P53
P52
P51
P50
XXXXXXXX
B
R/W
7
6
5
4
3
2
1
0
PDR6
Address: 000005
H
P67
P66
P65
P64
P63
P62
P61
P60
XXXXXXXX
B
R/W
7
6
5
4
3
2
1
0
PDR7
Address: 000004
H
P70
-------X
B
R/W
7
6
5
4
3
2
1
0
PDR8
Address: 00000B
H
P85
P84
P83
P82
P81
P80
--XXXXXX
B
R/W
7
6
5
4
3
2
1
0
PDRA
Address: 000009
H
PA6
PA5
PA4
PA3
PA2
PA1
PA0
-XXXXXXX
B
R/W
7
6
5
4
3
2
1
0
PDRB
Address: 000008
H
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
XXXXXXXX
B
R/W
7
6
5
4
3
2
1
0
PDRE
Address: 000012
H
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
XXXXXXXX
B
R/W
7
6
5
4
3
2
1
0
PDRF
Address: 000013
H
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
XXXXXXXX
B
R/W
Initial value
Access
Initial value
Access
Initial value
Access
Initial value
Access
Initial value
Access
Initial value
Access
Initial value
Access
Initial value
Access
Initial value
Access
Initial value
Access
Initial value
Access