FUJITSU MB91F109 FR30 - Manual (Page 451)

427
INDEX
bus control acquisition ......................................... 193
bus control release............................................... 193
bus converter, 32 bits - 16 bits............................... 32
bus converter, Harvard-Princeton .......................... 32
bus interface ............................................................ 2
bus interface register ........................................... 113
bus interface, block diagram of ............................ 114
bus interface, feature of ....................................... 112
bus mode ............................................................... 69
bus size specification ........................................... 117
bus width combination ......................................... 129
byte access .......................................... 142, 148, 153
byte ordering .......................................................... 42
C
CAS before RAS (CBR) refresh ........................... 191
cascade mode...................................................... 243
CBR refresh, automatic wait cycle of ................... 192
change-point detection......................................... 296
change-point detection data register (BSDC) ...... 294
characteristic............................................................ 2
characteristic of CPU architecture ......................... 30
chip select area and bus interface ....................... 116
chip select area, setting ....................................... 115
CLK synchronous mode............................... 243, 265
CLK synchronous mode, format of data
transferred in.............................................. 258
clock control ............................................................. 4
clock doubler function, disabling .......................... 105
clock doubler function, enabling........................... 105
clock doubler function, note on enabling or
disabling..................................................... 106
clock generator and controller block diagram ........ 75
clock generator and controller, register of.............. 74
clock system reference diagram .......................... 109
clock, how to choose............................................ 194
code used in timing chart ..................................... 342
command operation ............................................. 361
communication, end of......................................... 259
communication, start of ........................................ 259
compare operation instruction.............................. 410
condition code register (CCR)................................ 39
connection to external device, example of... 146, 150
continuous conversion mode ............................... 276
continuous transfer .............................................. 340
continuous transfer mode .................................... 336
continuous transfer mode for 16/8-bit data, transfer
stop in (both address are unchanged) ....... 348
continuous transfer mode for 16/8-bit data, transfer
stop in (either address is unchanged) ........347
control register......................................................236
control status register (ADCS), bit function of ......270
control status register (ADCS), configuration of ...270
control status register (PCNH, PCHL), bit
function of ...................................................304
control status register (PCNH, PCHL),
configuration of ...........................................304
control status register (TMCSR), bit function of....284
control status register (TMCSR), configuration of 284
conversion data protection function......................278
convert-and-stop mode.........................................277
coprocessor control instruction.............................423
coprocessor error trap ............................................67
coprocessor nonexistent trap .................................67
counter state.........................................................289
CPU ........................................................................31
CPU architecture. characteristic of .........................30
CPU status, pin status for each ............................384
crystal oscillation circuit ..........................................27
D
data access ....................................................43, 399
data bus width ..............................................142, 149
data bus width and control signal,
relationship between ..................................139
data direction register (DDR), configuration of .....204
data format ...................................................141, 147
data register (ADCR), configuration of .................275
data register, change-point detection (BSDC)......294
data transfer block for 16/8-bit data......................345
data transferred in asynchronous (start-stop)
mode, format of ..........................................257
data transferred in CLK synchronous mode,
format of .....................................................258
debugger, emulator and monitor ..........................402
debugger, simulator..............................................402
delay slot ................................................................53
delay slot, branch instruction with...........................48
delayed interrupt control register (DICR), bit
function of ...................................................221
delayed interrupt control register (DICR),
configuration of ...........................................221
delayed interrupt module block diagram...............220
delayed interrupt module register .........................220
delayed-branch instruction ...................................416
delayed-branch macro instruction, 20-bit .............419
delayed-branch macro instruction, 32-bit .............421
descriptor access block ........................................343