FUJITSU MB91F109 FR30 - Manual (Page 105)

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3.5 Timebase Timer Clear Register (CTBR)
3.5 Timebase Timer Clear Register (CTBR)
The timebase timer clear register (CTBR) clears the timebase timer to 0 for
initialization.
■ Configuration of the Timebase Timer Clear Register (CTBR)
The configuration of the timebase timer clear register (CTBR) is shown below:
■ Bit Functions of the Timebase Timer Clear Register (CTBR)
[bit 07 to bit 00]
When A5
H
and 5A
H
are written successively to this register, the timebase timer is cleared to
0 immediately after 5A
H
is written. The value read from this register is undefined. There is
no restriction on the time interval between A5
H
and 5A
H
writing.
Clearing the timebase timer using this register temporarily changes the oscillation stabilization
wait time, watchdog cycle, and cycles of the peripherals using the time base.
07 06 05 04 03 02 01 00
00000483
H
D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXX W
Access Initial value