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1 timing charts of the descriptor access block – FUJITSU MB91F109 FR30 User Manual

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15.9 DMAC Timing Charts

15.9.1 Timing Charts of the Descriptor Access Block

This section shows timing charts of the descriptor access block.

■

Descriptor Access Block

❍

Required pin input mode: level, descriptor address: external

❍

Required pin input mode: level, descriptor address: internal

(A)

CLK

DREQn

RDXD

WRnX
DACK
EOP

#2H

#2H

S

S

#1H

#1L

#1H

#1L

#0L

#0H

#0L

#0H

#2L

#2L

Addr pin

Data pin

(A)

Interanl KB

CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

S

S

DACK

EOP

See also other documents in the category FUJITSU Hardware: