FUJITSU MB91F109 FR30 - Manual (Page 129)

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3.14 Clock Doubler Function
3.14 Clock Doubler Function
As the internal operating frequency goes higher, the external bus timing normally
becomes more complicated. To prevent this, the ratio of the external bus frequency to
the internal operating frequency can be adjusted to 1 to 2 (1 : 2).
This model does not support this function.
■ Enabling the Clock Doubler Function
The clock doubler function is enabled by setting the GCR DBLON bit to 1. When DBLON is set
to 1, the system waits for all C-BUS accesses to be finished and then switches the external bus
clock. Thus, there is a small time lag before the switching is completed, but the timing for
switching can be determined by the GCR DBLAK value.
When the clock doubler function is enabled, the CPU clock gear becomes 1/1 regardless of the
GCR setting.
This device permits a frequency up to double the oscillation to be set as the external bus
operating frequency. Therefore, code as follows to enable the clock doubler function:
[Example]
■ Disabling the Clock Doubler Function
The clock doubler function is disabled by setting the GCR DBLON bit to 0. The CPU clock gear
changes from 1/1 back to the setting in the CCK bit of the GCR register simultaneously
DOUBLER-ON
LDI:20 #GCR,R0
BORL #0001B,@R0 ; Switches to the divide-by-two clock (CHC
= 1)
BORH #0001B,@R0 ; Enables the clock doubler function
(DBLON = 1)
LOOP
BTSTH #0010B,@R0 ; Checks DBLAK
BEQ LOOP ; Loops until DBLAK becomes 1
BANDL #1110B,@R0 ; Switches to the PLL clock (CHC = 0)