Altera RapidIO MegaCore Function - Manual (Page 98)

4–52 Chapter 4: Functional Description
Logical Layer Modules
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
Input/Output Avalon-MM Slave Module Timing Diagrams
Figure 4–27 shows the timing dependencies on the Avalon-MM slave interface for an
outgoing RapidIO NREAD request. Figure 4–28 shows the timing dependencies on the
Avalon-MM slave interface for an outgoing NWRITE transaction. Both transaction
requests originate on the Avalon-MM interface of the slave module. The timing
diagrams in
“Input/Output Avalon-MM Master Module Timing Diagrams” on
page 4–40 show the same transactions after they are transmitted on the RapidIO link
and received by an Altera RapidIO IP core link partner, when they are sent out as
Avalon-MM requests by an Input/Output Avalon-MM master module in the partner
RapidIO IP core.
Figure 4–27. NREAD Transaction on the Input/Output Avalon-MM Slave Interface
sysclk
io_s_rd_chipselect
io_s_rd_waitrequest
io_s_rd_read
io_s_rd_address[31:0]
io_s_rd_readdatavalid
io_s_rd_readdata[31:0]
io_s_rd_burstcount[7:0]
io_s_rd_readerror
Adr0 Adr1
00000000 r0 r1 r2
01 02
Figure 4–28. NWRITE Transaction on the Input/Output Avalon-MM Slave Interface
sysclk
io_s_wr_chipselect
io_s_wr_waitrequest
io_s_wr_write
io_s_wr_address[31:0]
io_s_wr_writedata[31:0]
io_s_wr_byteenable[3:0]
io_s_wr_burstcount[7:0]
00000000 AdrA AdrB
w0 w1 w2 w3 w4 w5
F
02 04