Simulating ip cores, Simulating the testbench with the vcs simulator, Simulating ip cores –4 – Altera RapidIO MegaCore Function User Manual
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Chapter 2: Getting Started
Simulating IP Cores
RapidIO MegaCore Function
August 2014
Altera Corporation
User Guide
Simulating IP Cores
The Quartus II software supports RTL- and gate-level design simulation of Altera IP
cores in supported EDA simulators. Simulation involves setting up your simulator
working environment, compiling simulation model libraries, and running your
simulation.
You can use the functional simulation model and the testbench or example design
generated with your IP core for simulation. The functional simulation model and
testbench files are generated in a project subdirectory. This directory may also include
scripts to compile and run the testbench. For a complete list of models or libraries
required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation
files and scripts. NativeLink launches your preferred simulator from within the
Quartus II software.
For more information about simulating Altera IP cores, refer to
volume 3 of the Quartus II Handbook.
Simulating the Testbench with the ModelSim Simulator
To simulate the RapidIO IP core testbench using the Mentor Graphics ModelSim
simulator, perform the following steps:
1. Start the ModelSim simulator.
2. For non-Arria 10 variations only, in ModelSim, change directory to
<your_ip>/simulation/submodules.
3. For non-Arria 10 variations only, type the following command to update the
simulation scripts in the simulator-specific directories:
do srio_simulator.tcl
r
4. Change directory to the location of the testbench script,
<your_ip>/simulation/mentor.
5. To set up the required libraries, compile the generated IP Functional simulation
model, and exercise the simulation model with the provided testbench, perform
one of the following steps:
a. For non-Arria 10 variations, type the following command:
do msim_setup.tcl
set TOP_LEVEL_NAME tb
ld
run -all
b. For Arria 10 variations, type the following command:
do msim_setup.tcl
set TOP_LEVEL_NAME
ld
run -all
Simulating the Testbench with the VCS Simulator
To simulate the RapidIO IP core testbench using the Synopsys VCS simulator, perform
the following steps: