Altera RapidIO MegaCore Function - Manual (Page 12)

1–4 Chapter 1: About This MegaCore Function
Device Family Support
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
■ Qsys support
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
■ Support for OpenCore Plus evaluation
Supported Transactions
The RapidIO IP core supports the following RapidIO transactions:
■ NREAD request and response
■ NWRITE request
■ NWRITE_R request and response
■ SWRITE request
■ MAINTENANCE read request and response
■ MAINTENANCE write request and response
■ MAINTENANCE port-write request
■ DOORBELL request and response
Device Family Support
Table 1–1 defines the device support levels for Altera IP cores.
Table 1–2 shows the level of support offered by the Rapid IO IP core for each Altera
device family.
Table 1–1. Altera IP Core Device Support Levels
FPGA Device Families
Preliminary support—The IP core is verified with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. It can be used in production designs with caution.
Final support—The IP core is verified with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family and can be used in production
designs.
Table 1–2. Device Family Support (Part 1 of 2)
Device Family Support
Arria ® II GX Final
Arria II GZ Final
Arria V (GX, GT, GZ, SX, and ST) Refer to the What’s New in Altera IP page of the Altera website.
Arria 10 Refer to the What’s New in Altera IP page of the Altera website.
Cyclone ® IV GX (1) Final
Cyclone V (GX, GT, SX, and ST) Refer to the What’s New in Altera IP page of the Altera website.
Stratix ® IV Final
Stratix IV GT Final