Altera RapidIO MegaCore Function - Manual (Page 79)

Chapter 4: Functional Description 4–33
Logical Layer Modules
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
The payload is written to a Tx Port Write Buffer starting at address 0x10210. This
buffer can store a maximum of 64 bytes. The port-write processor starts the packet
composition and transmission process after the PACKET_READY bit in the Tx Port Write
Control
register is set. The composed Maintenance port-write packet is sent to the
Transport layer for transmission.
Port-Write Reception
The Maintenance module receives a MAINTENANCE packet on the Rx Atlantic interface
from the Transport layer. The port-write processor handles MAINTENANCE packets with
a ttype value set to 4'b0100. The port-write processor extracts the following fields
from the packet header and uses them to write the appropriate content to registers Rx
Port
Write Control ( Table 6–36 on page 6–19 ) through Rx Port Write Buffer
( Table 6–38 on page 6–20 ):
■ wrsize
■ wdptr
■ payload
The wrsize and the wdptr determine the value of the PAYLOAD_SIZE field in the Rx
Port Write Status
register ( Table 6–37 on page 6–20 ). The payload is written to the
Rx Port Write Buffer starting at address 0x10260. A maximum of 64 bytes can be
written. While the payload is written to the buffer, the PORT_WRITE_BUSY bit of the Rx
Port
Write Status register remains asserted. After the payload is completely written
to the buffer, the interrupt signal sys_mnt_s_irq is asserted by the Concentrator on
behalf of the Port Write Processor. The interrupt is asserted only if the
RX_PACKET_STORED
bit of the Maintenance Interrupt Enable register ( Table 6–27 on
page 6–17 ) is set.
Maintenance Module Error Handling
The Maintenance Interrupt register (at 0x10080) and the Maintenance Interrupt
Enable
register (at 0x10084), described in Table 6–26 and Table 6–27 , determine the
error handling and reporting for MAINTENANCE packets.
The following errors can also occur for MAINTENANCE packets:
■ A MAINTENANCE read or MAINTENANCE write request time-out occurs and a
PKT_RSP_TIMEOUT
interrupt (bit 24 of the Logical/Transport Layer Error Detect
CSR, described in Table 6–52 on page 6–24 ) is generated if a response packet is not
received within the time specified by the Port Response Time-Out Control
register (
Table 6–7 on page 6–6 ).
■ The IO_ERROR_RSP (bit 31 of the Logical/Transport Layer Error Detect CSR) is set
when an ERROR response is received for a transmitted MAINTENANCE packet.
For information about how the time-out value is calculated, refer to Table 6–7 on
page 6–6 .
For more information about the error management registers, refer to Table 6–52 on
page 6–24 .
Input/Output Logical Layer Modules
This section describes the following Input/Output Logical layer modules: