Altera RapidIO MegaCore Function - Manual (Page 59)

Chapter 4: Functional Description 4–13
Physical Layer
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
The receiver uses the CCITT polynomial x 16 + x 12 + x 5 + 1 to check the 16-bit CRCs that
cover all packet header bits (except the first 6 bits) and all data payload, and flags
CRC and packet size errors.
Low-Level Interface Transmitter
The transmitter in the low-level interface transmits output to the RapidIO interface.
This module performs the following tasks:
■ Assembles packets and control symbols into a proper output format
■ Generates the 5-bit CRC to cover the 19-bit symbol and appends the CRC at the
end of the symbol
■ Transmits an idle sequence during port initialization and when no packets or
control symbols are available to transmit
■ Transmits outgoing multicast-event control symbols in response to user requests
■ Transmits status control symbols and the rate compensation sequence periodically
as required by the RapidIO specification
The low-level transmitter block creates and transmits outgoing multicast-event
control symbols. Each time the multicast_event_tx input signal changes value, this
block inserts a multicast-event control symbol in the outgoing bit stream as soon as
possible.
In 1.25, 2.5, and 3.125 Gbaud variations, the internal transmitters are not turned off
while the initialization state machine is in the SILENT state. Instead, while in SILENT
state, the transmitters send a continuous stream of K28.5 characters, all of the same
disparity. This behavior causes the receiving end to declare numerous disparity errors
and to detect a loss of lane_sync as intended by the specification.
In 5.0 Gbaud variations, the internal transmitters are turned off while the initialization
state machine is in the SILENT state. This behavior also causes the link partner to
detect the need to reinitialize the RapidIO link.
Transmitter Transceiver
The transmitter transceiver is an embedded megafunction in the Arria II GX,
Arria II GZ, Cyclone IV GX, or Stratix IV GX device, or an embedded Custom PHY IP
core in the Arria V, Cyclone V, or Stratix V device, or an embedded Arria 10 Native
PHY IP core in the Arria 10 device.
The transmitter transceiver implements the following process:
1. Multiplexes the 16-bit or 32-bit parallel input data to the transmitter to 8-bit data.
2. Performs 8B10B encoding on the 8-bit data to convert it to 10-bit code groups.
3. Serializes the 10-bit encoded data and sends it to differential output pins.
Protocol and Flow Control Engine
The Physical layer protocol and flow control engine uses a sliding window protocol to
handle incoming and outgoing packets.This block performs the following tasks:
■ Monitors incoming and outgoing packet ackIDs to maintain proper flow