Altera RapidIO MegaCore Function - Manual (Page 101)

Chapter 4: Functional Description 4–55
Logical Layer Modules
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Doorbell Message Generation
To generate a DOORBELL request packet on the RapidIO serial interface, follow these
steps, using the set of registers described in
“Doorbell Message Registers” on
page 6–26 :
1. Optionally enable interrupts by writing the value 1 to the appropriate bit of the
Doorbell Interrupt Enable register ( Table 6–66 ).
2. Optionally enable confirmation of successful outbound messages by writing 1 to
the COMPLETED bit of the Tx Doorbell Status Control register ( Table 6–65 ).
3. Set up the priority field of the Tx Doorbell Control register ( Table 6–60 ).
4. Write the Tx Doorbell register ( Table 6–61 ) to set up the DESTINATION_ID and
Information fields of the generated DOORBELL packet format.
1
Before writing to the Tx Doorbell register you must be certain that the Doorbell
module has available space to accept the write data. Ensuring sufficient space exists
avoids a waitrequest signal assertion due to a full FIFO. When the waitrequest
signal is asserted, you cannot perform other transactions on the DOORBELL Avalon-MM
slave port until the current transaction is completed. You can determine the combined
fill level of the staging FIFO and the Tx FIFO by reading the Tx Doorbell Status
register (
Table 6–62 ). The total number of Doorbell messages stored in the staging
FIFO and the Tx FIFO, together, is limited to 16 by the assertion of the
drbell_s_waitrequest
signal.
After a write to the Tx Doorbell register is detected, internal control logic generates
and sends a Type 10 packet based on the information in the Tx Doorbell and Tx
Doorbell
Control registers. A copy of the outbound DOORBELL packet is stored in the
Acknowledge RAM.
When the response to an outbound DOORBELL message is received, the corresponding
copy of the outbound message is written to the Tx Doorbell Completion FIFO (if
enabled), and an interrupt is generated (if enabled) on the Avalon-MM slave interface
by asserting the drbell_s_irq signal of the Doorbell module. The ERROR_CODE field in
the Tx Doorbell Completion Status register (
Table 6–64 ) indicates successful or error
completion.
The corresponding interrupt status bit is set each time a valid response packet is
received, and resets itself when the Tx Completion FIFO is empty. Software optionally
can clear the interrupt status bit by writing a 1 to this specific bit location of the
Doorbell
Interrupt Status register ( Table 6–67 ).
Upon detecting the interrupt, software can fetch the completed message and
determine its status by reading the Tx Doorbell Completion (
Table 6–63 ) register and
Tx Doorbell Completion Status register ( Table 6–64 ), respectively.
An outbound DOORBELL message is assigned a time-out value based on the VALUE field
of the Port Response Time-Out Control register (
Table 6–7 on page 6–6 ) and a
free-running counter. When the counter reaches the time-out value, if the DOORBELL
transaction has not yet received a response, the transaction times out. Refer to
Table 6–7 for information about how the time-out value is calculated.