Altera RapidIO MegaCore Function - Manual (Page 58)

4–12 Chapter 4: Functional Description
Physical Layer
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
Low-level Interface Receiver
The receiver in the low-level interface receives the input from the RapidIO interface,
and performs the following tasks:
■ Separates packets and control symbols
■ Removes idle sequence characters
■ Detects multicast-event and stomp control symbols
■ Detects packet-size errors
■ Checks the control symbol 5-bit CRC and asserts symbol_error if the CRC is
incorrect
Receiver Transceiver
The receiver transceiver is an embedded megafunction in the Arria II GX, Arria II GZ,
Cyclone IV GX, or Stratix IV GX device, or an embedded Custom PHY IP core in the
Arria V, Cyclone V, or Stratix V device, or an embedded Arria 10 Native PHY IP core
in the Arria 10 device. The receiver transceiver implements the following process:
1. Feeds serial data from differential input pins to the CRU to detect clock and data.
2. Deserializes recovered data into 10-bit code groups.
3. Sends the code groups to the pattern detector and word-aligner block to detect
word boundaries.
4. Performs 8B10B decoding on properly aligned 10-bit code groups to convert them
to 8-bit characters.
5. Converts 8-bit characters to 16-bit or 32-bit data in the 8-to-16 or 8-to-32
demultiplexer.
CRC Checking and Removal
The RapidIO specification states that the Physical layer must add a 16-bit CRC to all
packets. The size of the packet determines how many CRCs are required.
■ For packets of 80 bytes or fewer—header and payload data included—a single
16-bit CRC is appended to the end of the packet.
■ For packets longer than 80 bytes—header and payload data included—two 16-bit
CRCs are inserted; one after the 80th transmitted byte and the other at the end of
the packet.
Two null padding bytes are appended to the packet if the resulting packet size is not
an integer multiple of four bytes.
In variations of the RapidIO IP core that include the Transport layer, the Transport
layer removes the CRC after the 80
th byte (if present), but does not remove the final
CRC nor the padding bytes. Therefore, a packet sent to the Avalon-ST pass-through
receiver interface by the Transport layer is two or four bytes longer than the
equivalent packet received by the Transport layer from the Avalon-ST pass-through
interface. When processing the received packets, the Logical layer modules must
ignore the final CRC and padding bytes (if present). In variations of the RapidIO IP
core that include only the Physical layer, the 80
th byte CRC of a received packet is not
removed.