Altera RapidIO MegaCore Function - Manual (Page 109)

Chapter 4: Functional Description 4–63
Error Detection and Management
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
■ Missing response (time-out)
■ Response with ERROR status
The RapidIO IP core implements part of the optional Error Management Extensions
as defined in Part 8 of the RapidIO Interconnect Specification Revision 2.1. However,
because the registers defined in the Error Management Extension specification are not
all implemented in the RapidIO IP core, the error management registers are mapped
in the Implementation Defined Space instead of being mapped in the Extended
Features Space.
The following Error Management registers are implemented in the RapidIO IP core
and provide the most useful information for error management:
■ Logical/Transport Layer Error Detect CSR ( Table 6–52 )
■ Logical/Transport Layer Error Enable CSR ( Table 6–53 )
■ Logical/Transport Layer Address Capture CSR ( Table 6–54 )
■ Logical/Transport Layer Device ID Capture CSR ( Table 6–55 )
■ Logical/Transport Layer Control Capture CSR ( Table 6–56 )
1
For more information about these registers, refer to their descriptions in “Error
Management Registers” on page 6–24 .
When enabled, each error defined in the Error Management Extensions triggers the
assertion of an interrupt on the sys_mnt_s_irq output signal of the System
Maintenance Avalon-MM slave interface and causes the capture of various packet
header fields in the appropriate capture CSRs.
In addition to the errors defined by the RapidIO specification, each Logical layer
module has its own set of error conditions that can be detected and managed.
Maintenance Avalon-MM Slave
The Maintenance Avalon-MM slave module creates request packets for the
Avalon-MM transaction on its slave interface and processes the response packets that
it receives. Anomalies are reported through one or more of the following three
channels:
■ Standard error management registers
■ Registers in the implementation defined space
■ The Avalon-MM slave interface’s error indication signal
The following sections describe these channels.
Standard Error Management Registers
The following standard defined error types can be declared by the I/O Avalon-MM
slave module. The corresponding error bits are then set and the required packet
information is captured in the appropriate error management registers.
■ IO Error Response is declared when a response with ERROR status is received for a
pending MAINTENANCE read or write request.