Altera RapidIO MegaCore Function - Manual (Page 25)

Chapter 2: Getting Started 2–3
Files Generated for Altera IP Cores
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
The RapidIO IP core does not generate an example design. The RapidIO installation
directory includes a static design example available in a separate location. Refer to
Chapter 8, Qsys Design Example .
Files Generated for Altera IP Cores
The Quartus II software version 14.0 Arria 10 Edition and later generates the
following output file structure for Altera IP cores:
In Arria 10 variations, the testbench files appear in
<your_ip>/altera_rapidio_140/sim/tb.
The Quartus II software generates the <your_testbench_name>_tb directory if you click
Generate > Generate Testbench
in the RapidIO parameter editor. However, the
resulting testbench is composed of BFM stubs and does not exercise the RapidIO IP
core in any meaningful way. The Altera-provided RapidIO IP core testbench for Arria
10 variations that is described in
Chapter 7, Testbenches is generated when you
generate a simulation model of the IP core. This Arria 10 testbench is available in
<your_ip>/altera_rapidio_140/sim/tb.
The RapidIO IP core does not generate an example design. The static design example
included in the RapidIO installation directory does not function correctly with Arria
10 IP core variations.
Figure 2–2. IP Core Generated Files
<Project Directory>
<your_testbench>_tb.csv
<your_testbench>_tb.spd
sim - IP core simulation files
<your_testbench>_tb - Simulation testbench files
<your_testbench>_tb
<your_ip> - IP core variation files
<your_ip>.cmp - VHDL component declaration file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists IP synthesis files
<your_ip>.sip - Lists files for simulation
synth - IP synthesis files
<your_ip>.v or .vhd - Top-level IP synthesis file
sim - IP simulation files
1
<your_ip>.v or .vhd - Top-level simulation file
<EDA_tool_name> - Simulator setup scripts
<simulator_setup_scripts>
<IP subcore library> - IP subcore files
<HDL files>
sim
<your_ip>.qsys - System or IP integration file
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
<your_ip>_generation.rpt - IP generation report
<your_ip>.debuginfo - IP generation report
<your_ip>.html - Contains memory map
<your_ip>.bsf - Block symbol schematic
<your_ip>.spd - Combines individual simulation startup scripts
1
<your_ip>_tb.qsys - Testbench system file
1
<your_ip>.sopcinfo - Software tool-chain integration file
1. If supported and enabled for your IP variation