Avalon-mm burstcount – Altera RapidIO MegaCore Function User Manual
Page 94
4–48
Chapter 4: Functional Description
Logical Layer Modules
RapidIO MegaCore Function
August 2014
Altera Corporation
User Guide
Translation Window 2
An Avalon-MM address in which the two most significant bits have a value of 2'b11
matches window 2. The RapidIO transaction corresponding to the Avalon-MM
operation has a destination ID value of 0xCC. This value corresponds to processing
endpoint 2.
shows address translation window 2.
Avalon-MM Burstcount and Byteenable Encoding in RapidIO Packets
The RapidIO IP core converts Avalon-MM transactions to RapidIO packets. The
Avalon-MM burst count, byteenable, and, in 32-bit variations, address bit 2 values are
translated to the RapidIO packets' read size, write size, and word pointer fields.
For information about the packet size encoding used in the conversion process for
32–bit datapath read requests, refer to
. For information about the encoding
for 32-bit datapath write requests, refer to
. For information about the
encoding for 64-bit datapath conversion, refer to
.
Figure 4–26. Translation Window 2
0x7555999
0x7555999
RapidIO Address [33:0]
{Avalon Address, N’b0}
1
0
0
0
Destination ID
Don’t Care
Don’t Care
0
2
3
3
000000000000000000..............00
Base (register 0x10420)
Mask (register 0x10424)
Offset (register 0x10428)
Control (register 0x1042C)
1
29
29
23
16
30
31
R
R
1
1
1
1
1
1
0
0
0
0
1
1
1
1
30
31
32
33
XAMO
0xCC
Table 4–11. Read Request Size Encoding (32-bit datapath) (Part 1 of 2)
Avalon-MM Values
RapidIO Values
burstcount
address[0]
(1'bx)
wdptr
(1'bx)
rdsize
(4'bxxxx)
1
1
0
1000
1
0
1
1000
2
0
0
1011
3–4
0
1
1011
5–8
0
0
1100
9–16
0
1
1100
17–24
0
0
1101
25–32
0
1
1101
33–40
0
0
1110