Altera RapidIO MegaCore Function - Manual (Page 194)

Info–2 Additional Information
Document Revision History
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
June 2014
(continued)
Continued on
next page
14.0
■ Removed support for Physical-layer only variations. The RapidIO IP core no longer
supports Physical-layer only variations.
■ Removed information about the Atlantic interface, which is no longer visible at the top
level. Removed information from
“OpenCore Plus Time-Out Behavior” on page 1–13 ,
Chapter 4, Functional Description , Chapter 5, Signals , and Chapter 7, Testbenches . For
example, modified the description of the Atlantic interface to retain only a description of
the Physlcal layer buffers.
■ Removed information about clocking, reset, and testbench for Physical-layer only
variations. Removed information from
Chapter 4, Functional Description and Chapter 7,
Testbenches . In Chapter 4, Functional Description , modified Figure 4–5 on page 4–11 ,
combined separate clocking sections for the Physlcal-layer only variations and other
variations and combined separate reset sections. In
Chapter 7, Testbenches , removed
information about the Physical-layer only testbench.
■ Removed the PHY Maintenance Avalon-MM slave interface signals (phy_mnt_s_clk,
phy_mnt_s_chipselect, phy_mnt_s_waitrequest, phy_mnt_s_read,
phy_mnt_s_write, phy_mnt_s_addresss, phy_mnt_s_writedata,
phy_mnt_s_readdata ). This interface is no longer a top-level interface. In variations
with a Transport layer, software accesses the Physical layer registers through the
system maintenance Avalon-MM slave interface instead.
■ Removed the “Calculating Resource Utilization for Modular Configurations” appendix.
■ Corrected the description of the atxwlevel, atxovf, and arxwlevel Physical-layer
buffer status output signals to indicate they are available. These signals were previously
described incorrectly as being available only in Physical-layer-only variations.
■ Added section “Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP
Core Instances” on page 2–12 . This section describes an additional requirement for
ensuring a design with multiple RapidIO IP core instances functions correctly.
■ Added new section “Avalon-MM Interface Widths in the RapidIO IP Core” on page 4–1 .
■ Clarified that sys_mnt_s_address, mnt_s_address, and drbell_s_address are word
addresses and not byte addresses. They each address a four-byte (32-bit) word. Modified
Maintenance TX address window translation calculation accordingly in
“Maintenance
Module” .
■ Corrected the width of mnt_s_address to 24 bits in Table 5–13 on page 5–11 and in the
Maintenance TX address window translation calculation description in “Maintenance
Module” .
■ Clarified that io_s_wr_address and io_s_rd_address are word addresses (and not
byte addresses) in RapidIO 1x variations, and are double-word addresses in 2x and 4x
variations, in
Table 5–16 on page 5–12 and Table 5–17 on page 5–13 , respectively.
Corrected header and note in Table 4–11 on page 4–48 and Table 4–12 on page 4–49 to
specify that the bit that provides the wdptr information is bit [0] rather than bit [2].
Corrected address window translation calculation and examples accordingly in
“Input/Output Avalon-MM Slave Module” on page 4–41 .
■ Updated parameter descriptions in Chapter 3, Parameter Settings .
■ Updated capitalization and minor changes in parameter names.
■ Transceiver selection is no longer modifiable. The remaining supported device families
do not support an external transceiver option.
■ Removed the Transceiver Configuration option.
■ Removed Enable Transport Layer parameter. The RapidIO IP core no longer supports
Physical-layer only variations: all variations have a Transport layer.
■ Removed EDA Settings and Summary sections. These tabs no longer exist in the
RapidIO parameter editor in the new Quartus II software v14.0 IP design flow.
Date Version Changes