Altera RapidIO MegaCore Function - Manual (Page 185)

Chapter 8: Qsys Design Example 8–11
Running Qsys
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
2. On the File menu, click Save and type rio_sys to save the Qsys system in the
rio_sys.qsys file.
Figure 8–4 shows the completed Qsys system.
Generating the System
After you create your system with all the required components and connections and
you have resolved any errors, generate the system by following these steps:
1. Click the Generation tab.
2. For Create simulation model, select Verilog.
3. For Create testbench Qsys system, select None.
4. For Create testbench simulation model, select None.
5. Turn off Create HDL design files for synthesis. This Qsys system cannot run on
hardware.
6. Turn off Create block symbol file (.bsf) to expedite the generation process.
7. Click Generate to start the generation process.
rapidio_0 sys_mnt_slave 0x00000000
onchip_mem... s1 0x00000000
Table 8–7. Assign Addresses (Part 2 of 2)
Port Name Base Address
Figure 8–4. Complete Qsys Example System