Altera RapidIO MegaCore Function User Manual
Page 90
4–44
Chapter 4: Functional Description
Logical Layer Modules
RapidIO MegaCore Function
August 2014
Altera Corporation
User Guide
Let avalon_address[31:0] be the 32-bit Avalon-MM address, and rio_addr[33:0] be
the RapidIO address, in which rio_addr[33:32] is the 2-bit wide xamsbs field,
rio_addr[31:3]
is the 29-bit wide address field in the packet, and rio_addr[2:0] is
implicitly defined by wdptr and rdsize or wrsize.
Let base[31:0], mask[31:0], and offset[31:0] be the values defined by the three
corresponding window-defining registers. The least significant 3 bits of base, mask,
and offset are fixed at 3’b000 regardless of the content of the window-defining
registers.
Let xamo be the Extended Address MSBits Offset field in the Input/Output Slave
Window n Offset
register (the two least significant bits of the register).
Starting with window 0, find the first window for which
(({address,Nb’0}
& mask) == (base & mask))
where N is 2 in 1x variations and 3 in 2x and 4x variations.
Let
rio_addr
[33:3] = {xamo, (offset [31:3] & mask [31:3]) |
({avalon_address,Nb’0} [31:3]])}
If the address matches multiple windows, the lowest number window register set is
used. The Avalon-MM slave interface’s burstcount and byteenable signals determine
the values of wdptr and rdsize or wrsize, as described in
and Byteenable Encoding in RapidIO Packets” on page 4–48
The priority and DESTINATION_ID fields are inserted from the control register.
If the address does not match any window the following events occur:
■
An interrupt bit, either WRITE_OUT_OF_BOUNDS or READ_OUT_OF_BOUNDS in the
Input/Output
Slave Interrupt register (
), is set.
■
The interrupt signal sys_mnt_s_irq is asserted if enabled by the corresponding bit
in the Input/Output Slave Interrupt Enable register (
■
The COMPLETED_OR_CANCELLED_WRITES field of the Input/Output Slave RapidIO
Write Requests
register is incremented if the transaction is a write request.
An interrupt is cleared by writing 1 to the interrupt register’s corresponding bit
location.