Altera RapidIO MegaCore Function - Manual (Page 47)

August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
4. Functional Description
Interfaces
The Altera RapidIO IP core supports the following interfaces:
■ RapidIO Interface
■ Avalon Memory Mapped (Avalon-MM) Master and Slave Interfaces
■ Avalon Streaming (Avalon-ST) Interface
RapidIO Interface
The RapidIO interface complies with revision 2.1 of the RapidIO ® serial interface
standard described in the RapidIO Trade Association specifications. The protocol is
divided into a three-layer hierarchy: Physical layer, Transport layer, and Logical layer.
f
More detailed information about the RapidIO interface specification is available from
the RapidIO Trade Association website at
www.rapidio.org .
Avalon Memory Mapped (Avalon-MM) Master and Slave Interfaces
The Avalon-MM master and slave interfaces execute transfers between the RapidIO IP
core and the system interconnect. The system interconnect allows you to use the Qsys
system integration tool to connect any master peripheral to any slave peripheral,
without detailed knowledge of either the master or slave interface. The RapidIO IP
core implements both Avalon-MM master and Avalon-MM slave interfaces.
f For more information about the Avalon-MM interface, refer to Avalon Interface
Specifications .
Avalon-MM Interface Widths in the RapidIO IP Core
The RapidIO IP core has multiple Avalon-MM interfaces. The width of the data bus
varies with the interface and with the RapidIO IP core mode.
■ I/O Logical layer master and slave interfaces have a databus width of 32 bits in 1x
variations and a databus width of 64 bits in 2x and 4x variations.
■ Maintenance module has a databus width of 32 bits.
■ Doorbell module has a databus width of 32 bits.
Avalon-MM Interface Byte Ordering
The RapidIO protocol uses big endian byte ordering, whereas Avalon-MM interfaces
use little endian byte ordering.
Table 4–1 shows the byte ordering for the Avalon-MM
and RapidIO interfaces.