Altera RapidIO MegaCore Function - Manual (Page 82)

4–36 Chapter 4: Functional Description
Logical Layer Modules
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
Figure 4–18 shows a block diagram of the I/O master‘s window translation.
RapidIO Packet Data wdptr and Data Size Encoding in Avalon-MM
Transactions
The RapidIO IP core converts RapidIO packets to Avalon-MM transactions. The
RapidIO packets’ read size, write size, and word pointer fields are translated to the
Avalon-MM burst count and byteenable values.
Figure 4–18. I/O Master Window Translation
Note to Figure 4–18 :
(1) These bits must have the same value in the initial RapidIO address and in the window base.
Initial
RapidIO Address
0x00000000 0x000000000
Base
Offset
Window
0xFFFFFFF8
0x3FFFFFFF8
Don’t Care
Don’t Care
33
Window Base
Window Mask
Window Offset
Resulting
Avalon-MM Address
0 2 3
0 2 3
31
31
XAMB
XAMM
(1)
(1)
Avalon-MM
Address Space
RapidIO
Address Space
Window Size
11111111.........................11 000000000000000..............00